What is Dynamatic?

Dynamatic is an academic, open-source high-level synthesis compiler that produces synchronous dynamically-scheduled circuits from C/C++ code. Dynamatic generates synthesizable RTL which currently targets Xilinx FPGAs and delivers significant performance improvements compared to state-of-the-art commercial HLS tools in specific situations (e.g., applications with irregular memory accesses or control-dominated code). The fully automated compilation flow of Dynamatic is based on LLVM. It is customizable and extensible to target different hardware platforms and easy to use with commercial tools such as Vivado (Xilinx) and Modelsim (Mentor Graphics).

Why dynamic scheduling?

To illustrate the limitations of standard HLS approaches, consider the code on the left of Figure 1. In this loop, there is a control flow decision (if) which depends on the actual data being read from arrays A[ ] and B[ ]. The operation which might take place in a specific iteration (s = s + d) introduces a dependency between iterations and delays the next iteration whenever the condition is true. Pic 01

Figure 1: Limitations of static scheduling.


When pipelining this loop, a typical HLS tool needs to create a static schedule—that is, a conservative execution plan for the various operations in the loop which is valid in every possible case. Such a schedule is shown on the top of Figure 1: in the example, the condition is true only for the second and third iteration but “space” is reserved in the schedule as if the condition were true everywhere. Obviously, a good schedule is the bottom one: the operations of different iterations are overlapped as much as possible and the parallelism is reduced only when the dependency is actually there (that is, when the addition is executed). This schedule can be achieved by the dynamically scheduled circuit on the right: in this circuit, components exchange data as soon as all conditions for execution are satisfied and the schedule is adapted at runtime to particular data and control outcomes. Such behavior, realized in Dynamatic, is beyond what a statically scheduled HLS tool can achieve.

Publications

Lana Josipović, Andrea Guerrieri, and Paolo Ienne. Dynamatic: From C/C++ to Dynamically-Scheduled Circuits. Invited tutorial. In Proceedings of the 28th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Seaside, Calif., February 2020

Lana Josipović, Shabnam Sheikhha, Andrea Guerrieri, Paolo Ienne, and Jordi Cortadella. Buffer placement and sizing for high-performance dataflow circuits. In Proceedings of the 28th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pages 186–96, Seaside, Calif., February 2020. Best Paper Award.

Jianyi Cheng, Lana Josipović, George A. Constantinides, Paolo Ienne, and John Wickerson. Combining dynamic & static scheduling in high-level synthesis. In Proceedings of the 28th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pages 288–98, Seaside, Calif., February 2020.

Lana Josipović, Atri Bhattacharyya, Andrea Guerrieri and Paolo Ienne. Shrink It or Shed It! Minimize the Use of LSQs in Dataflow Designs. In Proceedings of the 2019 International Conference on Field Programmable Technology, Tianjin, December 2019.

Lana Josipović, Andrea Guerrieri, and Paolo Ienne. Speculative dataflow circuits. In Proceedings of the 27th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pages 162-71, Seaside, Calif., February 2019.

Lana Josipović, Radhika Ghosal, and Paolo Ienne. Dynamically scheduled high-level synthesis. In Proceedings of the 26th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pages 127-36, Monterey, Calif., February 2018. Best Paper Award Nominee.

Lana Josipović, Philip Brisk, and Paolo Ienne. From C to elastic circuits. In Proceedings of the 51st Annual Asilomar Conference on Signals, Systems, and Computers, pages 121-25, Pacific Grove, Calif., October 2017.

Lana Josipović, Philip Brisk, and Paolo Ienne. An out-of-order load-store queue for spatial computing. In Proceedings of the International Conference on Compilers, Architectures, and Synthesis for Embedded Systems, Seoul, Korea, October 2017. See ACM TECS paper below. Best Paper Award Nominee.

Lana Josipović, Philip Brisk, and Paolo Ienne. An out-of-order load-store queue for spatial computing. ACM Transactions on Embedded Computing Systems (TECS), 16(5s):125:1–125:19, September 2017.

Try it!

Dynamatic is released as open source under MIT license.
Three different version are available for download: source code, auto-install package, and the pre-installed virtual machine. For details on using the tool, please refer to the Dynamatic tutorial paper. (slides, exercises)

Icon

Source Code

Browse Dynamatic's source code. You can download and compile manually the packages.

Dynamatic on Github

Icon

Auto-installer package

Download and install automatically Dynamatic on your machine.


Dynamatic Installer

Icon

Virtual Machine

Download the virtual machine with Dynamatic pre-installed.


Dynamatic VM v1.1
VM setup instructions

Team

Dynamatic has been developed at Processor Architecture Laboratory, at École Polytechnique Fédérale de Lausanne (EPFL), in Lausanne, Switzerland. The Dynamatic team invites the community to try out the first generation of our Dynamically Scheduled High-Level Synthesis

Interested to contribute? Write us an email at name.surname@epfl.ch. We will be glad to reply to your questions!

Pic 01

Lana Josipović

Pic 02

Andrea Guerrieri

Pic 01

Paolo Ienne